While key drivers for CMOS scaling have been to reduce transistor cost and to improve digital performance, conventional RF/analog designs do not benefit significantly. By going from 180nm to 28nm CMOS, power supply voltage is reduced almost to half while MOS threshold voltage (Vth) has not changed considerably. Therefore, the available precious voltage headroom for RF/analog design is now reduced dramatically. Considering also the reduced MOS intrinsic gain and its saturation linearity, RF/analog design is becoming generally more difficult, time-consuming, and costly.
In Qualinx, we utilize Digital/Discrete-time RF (DRF) techniques and building blocks to avoid using complicated analog techniques, especially at deep nano-scale CMOS nodes. As a result, wireless receivers developed by Qualinx can fully operate at very low supply voltages with incredibly low power consumption. As the technology scales, Qualinx RF transceivers experience improved performance, less power consumption, and lower cost, just like digital circuits!