IPGNSSBBP300

GNSS Baseband Processor


IPGNSSBBP300

GNSS Baseband Processor


IPGNSSBBP300

GNSS Baseband Processor



IP Description

The IPGNSSBBP300 is a digital baseband processor IP designed for SoC integration. During development of this IP, special attention is paid to low power consumption and makes it a perfect fit for wearables, asset trackers, and IoT market.

The IPGNSSBBP300 supports several different L1-band constellations: GPS, GLONASS, BeiDou, Galileo, QZSS, and SBAS. This versatile IP is capable of receiving 3 different IF frequencies concurrently, meaning all L1 band constellations at the same time. With flexible and programmable coherent and non-coherent integrations per channel, IPGNSSBBP300 provides the highest acquisition and tracking sensitivity. This IP is also capable of generating a time-pulse output.

This IPGNSSBBP300 baseband processor does all required high speed GNSS signal processing. Next to this, it needs a general-purpose CPU, such as ARM Cortex-M0 (with very low MIPS requirement), to execute some low-speed software control algorithms. All necessary software APIs are included as part of IPGNSSBBP300 deliverables. The API functions can be executed in an already existed host CPU in an SoC implementation, based on a very simple cyclic timing requested by one IRQ signal. The IP has a standard AMBA AHB/APB interface and can be easily bridged to any other bus types.

The IPGNSSBBP300 hardware is reconfigurable thanks to its modular design. Depending on trade-offs between power/area and performance, number of processing Paths can be set from 5 (minimum) to hundreds. Each Path can be independently and individual programmed to:

  • become three parallel acquisition engines, or one channel tracking engine
  • receive each of the 3 IF frequencies
  • process each of the different constellations
  • have different coherent/non-coherent integrations
  • have different acquisition CodePhase search range
  • have different acquisition Doppler search range
  • be turned on/off at a programmable time

These versatility of this GNSS processor, allows to have a very efficient firmware with flexibility of ultra-low-power consumption mode to high performance mode. The timely turn-on/off feature of this IP allow cyclic tracking operation of the baseband and RF/Analog frontend that leads to significantly reduced system power consumption. The same processing hardware has the capability of making tasks parallel and distributed. For example, one can choose between parallel acquisition of all target constellations equally, or dedicate all resources to one constellation first (e.g. GPS) and then all resources to another one (e.g. GLONASS). Also, in re-acquisition, one can use all available resources in parallel for only few satellites: CodePhase search range of each satellite can be split and distributed between different Paths.

FPGA evaluation and development kit is available with 34 Paths implemented. With ready-to-use APIs, signal acquisition and tracking functionalities can be done, and raw tracking data is easily extracted.

Features

  • Multi-Constellation Support
    GPS, GLONASS, Beidou, Galileo
  • Concurrent Reception: all constellations
  • Ultra-Low Power Consumption
  • Designed for SoC Integration
  • High Sensitivity
  • Small Die Area
  • Time-Pulse Output
  • Scalable Engines for Power/Performance Trade-off
  • Low-MIPS General Purpose CPU Requirement
  • AMBA AHB/APB Bus Compliant

Applications

  • Wearables
  • Asset Trackers
  • IoT Sensor Nodes
  • Cameras
  • Consumer Mobile Products

Deliverables

  • Fully synthesizable RTL or GTECH
  • Test benches
  • API Library
  • FPGA Evaluation Board
  • Technical documents