Today, we are pleased to announce that RF/Analog Front-End of QLX300 is successfully tested. Signal path of this Ultra Low-Power GNSS SoC from antenna input to ADC outputs is fully functional while the Digital PLL generates precise clocks driving mixer, Discrete-Time filters, and the data converter. We are able to program and configure different parts of the frond-end through hundreds of registers controlled by an integrated ARM-Cortex processor. Our next step is full validation and characterization of QLX300.